AI/GPU-Accelerated Place&Routing Engine
Features
Place
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Global Route
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Timing Analysis
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Physical Optimization
End-to-end AI/GPU empowerment
Place
- GPU accelerated
- Timing driven
- Routability driven
- Region & density constraints
- AI-powered multi-objective optimization
Optimization
- GPU-accelerated STA with high correlation to golden tools
- GPU-accelerated Global Router and RC estimation
- GPU-accelerated optimization operators
- AI-powered design space exploration
Open & Adaptive
- Full PDK support down to 7nm
- Extensible python API with interactive shell and user-defined function
- Full observability & controllability via Python API, seamlessly integrate with any AI workflow
Our Vision
Agile, AI-Augmented Design Flows for Faster, Smarter Chips
We envision a future where digital chip design is no longer fragmented across siloed tools and manual iterations. By unifying AI/GPU-accelerated physical implementation with other front-end engines, enable a truly AI-Augmented, agile design flow. Further, intelligent AI Agents that autonomously explore the design space, co-optimize synthesis and placement decisions, and continuously learn from past projects.
Our mission is not to merely accelerate existing workflows, but to fundamentally reinvent how chips are designed — making intelligence, integration, and acceleration the new standard for digital implementation.